JEE Main 2021 · 16 March · evening · Single correct · +4 / −1
The following logic gate is equivalent to :
- (a) NOR Gate
- (b) NAND Gate
- (c) OR Gate
- (d) AND Gate
Answer and solution
Answer (a) NOR Gate
Solution
Physics sir · 3 steps
A NAND with both inputs tied is just a NOT gate. Replace those three first and the circuit becomes easy.
- Tied inputs. When both inputs of a NAND gate are joined, it gives A · A̅ = A̅. So the two input gates give A̅ and B̅, and the last gate inverts whatever it receives.
- Middle gate. The middle NAND gets A̅ and B̅. By De Morgan's theorem, A̅ · B̅̅ = A + B, so its output is an OR of the inputs.
Y = A + B̅
A B Middle output A + B Y 0 0 0 1 0 1 1 0 1 0 1 0 1 1 1 0 - So. The final tied NAND inverts A + B, so Y = A + B̅. Y is 1 only when both inputs are 0, which is a NOR gate, option (a).
The idea to keep. In any NAND-only circuit, first turn every tied-input NAND into a NOT gate. Then a NAND fed with inverted inputs is an OR gate, by De Morgan's theorem.
Answer from the NTA final answer key. Solution by PrepWiser.