JEE Main 2026 · 21 January · morning · Single correct · +4 / −1

The given circuit works as:

JEE Main PYQ figure
  1. (a) NOR gate
  2. (b) OR gate
  3. (c) AND gate
  4. (d) NAND gate
Answer and solution

Answer (d) NAND gate

Solution

Physics sir · 3 steps

A NOR gate with its inputs tied together is only a NOT gate, so follow the signal through each stage.

  1. Tied inputs. When both inputs of a NOR gate carry the same signal X, the output is X + X̅ = X̅. So the first two gates turn A into A̅ and B into B̅, and the last gate inverts whatever reaches it.
  2. Middle gate. The middle NOR receives A̅ and B̅. By De Morgan's theorem, A̅ + B̅̅ = A · B, so this stage gives AND. The final NOT then inverts it.

    Y = A̅ + B̅̅̅ = A · B̅

    ABA̅, B̅Middle NOROutput Y
    001, 101
    011, 001
    100, 101
    110, 010
  3. So. The output is 0 only when both inputs are 1, and 1 otherwise. That is the truth table of a NAND gate, option (d).

The idea to keep. NOR with tied inputs is NOT. Inverting both inputs of a NOR gives AND, and inverting both inputs of a NAND gives OR. Track the circuit stage by stage, then check your result against the truth table.

Answer from the NTA final answer key. Solution by PrepWiser.

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Asked about 170 times in JEE Main since 2020. This question is from 2026.